MeitY Launches ₹50 Lakh Blockchain India Challenge to Drive Digital Governance Innovation

Blockchain India Challenge, launched by the Ministry of Electronics and Information Technology (MeitY) in February 2026, is a national initiative designed to accelerate blockchain-based digital governance solutions. Here’s a clear breakdown:

Key Highlights

• Organizer: MeitY in collaboration with the Centre for Development of Advanced Computing (C-DAC).
• Launch Date & Venue: February 23, 2026, New Delhi.
• Objective: Harness blockchain and Web3 innovation to improve citizen-centric digital governance services.

Competition Structure

• Prototype Stage
  • Prize: ₹1.5 lakh each
  • Up to 40 participants
• Minimum Viable Product (MVP) Stage
  • Prize: ₹4 lakh each
  • Up to 30 participants
• Deployment Stage
  • Prize: ₹10 lakh each
  • Up to 20 participants

🏆 Grand Winners: ₹50 lakh each, across 10 use case categories.

Focus Areas

• Citizen-centric solutions for governance
• Transparency and efficiency in public services
• Leveraging blockchain for secure, scalable, and trusted digital platforms

Why It Matters

• This initiative positions India as a global leader in blockchain adoption for governance.
• Empowers startups to pilot real-world solutions that could redefine how citizens interact with government services.
• It’s not just about tech—it’s about trust, accountability, and innovation in public systems.

The details are available at https://challenge.cdac.in

Made-in-India AI Chip: IndieSemiC and C-DAC Sign MoU for Semiconductor Self-Reliance

Representative Image

• IndieSemiC and C-DAC Trivendrum Sign MoU for Semiconductor and Embedded Systems Collaboration
• IndieSemiC and C-DAC Trivendrum signed an MoU to collaborate on semiconductor and embedded system development.
• Collaboration to build an indigenous hardware and software ecosystem using THEJAS-32
• Focus on reducing reliance on imported chipsets and supporting India’s semiconductor goals

IndieSemiC, an India-based semiconductor design firm working on chip, RF, and system-level solutions, and the Centre for Development of Advanced Computing (C-DAC), a national R&D institution under MeitY focused on advanced computing and indigenous processor development, have signed a Memorandum of Understanding to collaborate on semiconductor and embedded system development. The collaboration includes joint development of an AI chip based on C-DAC Trivendrum’s 64-bit VEGA processor, integrated with an on-chip Neural Processing Unit (NPU). The chip is intended for applications including smart meters, smart city systems, industrial IoT, defence electronics, and sensor-based applications. The partnership also focuses on creating a fully indigenous hardware and software ecosystem using C-DAC Trivendrum’s THEJAS-32 microcontroller to develop a Made-in-India alternative to commonly used foreign microcontrollers.

IndieSemiC is an India-based semiconductor company engaged in the design and development of integrated circuits, RF modules, and system-level solutions for embedded and industrial applications. Under the MoU, C-DAC Trivendrum will provide processor intellectual property along with technical support for system-on-chip integration, validation, and testing, while IndieSemiC will lead the design, development, and system integration of chipsets and RF modules. The collaboration will support applications across industrial controllers, robotics, medical devices, consumer appliances, automotive electronics, and embedded systems, and aligns with the national objective of Atmanirbhar Bharat and semiconductor self-reliance.

Commenting on the collaboration, Jinal Shah, Co-Founder and CMO, IndieSemiC said, “This collaboration marks a structured step towards integrating indigenous processor intellectual property with system-level semiconductor design and execution. By combining C-DAC Trivendrum’s processor capabilities with IndieSemiC’s expertise in chip, RF, and system integration, the partnership aims to deliver application-ready semiconductor solutions for industrial, infrastructure, and strategic use cases. The engagement supports consistent design, validation, and deployment workflows that are aligned with national requirements for security, reliability, and domestic capability development.”

The collaboration will also focus on coordinated roadmaps for processor adoption, reference designs, and system validation to support faster deployment across target sectors. Joint efforts will address interoperability, software enablement, and testing to facilitate adoption by system integrators and product developers.

The MoU is valid for three years, with an option for extension by mutual consent. Any press release or public communication related to the collaboration will require prior approval from both parties.

About IndieSemiC

IndieSemiC is engaged in the design and development of semiconductor chipsets, RF modules, and embedded system solutions. The company focuses on system-on-chip design and integration for applications across industrial, automotive, consumer, and embedded electronics domains.

SmartSoC and CDAC's ChipIN Team Up to Offer Free Validation and Foundry Support for India’s Semiconductor Startups

SmartSoC Solutions Pvt. Ltd., a leading semiconductor and embedded engineering services company, has announced its collaboration with the ChipIN Center at Centre for Development of Advanced Computing (CDAC) to support India’s Design Linked Incentive (DLI) Programme. Through this initiative, SmartSoC will extend access to its advanced Post-Silicon Validation (PSV) services to DLI-registered startups and MSMEs on a pro-bono basis, while also offering multiple foundry options within the startup ecosystem.

This collaboration aims to address some of the most critical challenges faced by semiconductor startups in India— including access to diverse foundry services and world class backend validation and characterization infrastructure. By bridging these gaps, SmartSoC and CDAC will empower innovators to accelerate the journey from chip design to commercialization, reduce time-to-market, and strengthen their global competitiveness.

Bharath Desareddy, CEO of SmartSoC

“We are proud to be chosen as an engineering collaborator providing vital support to chip innovators in India. This is more than business—it’s our mission. We understand the tough journey from design to functional silicon. SmartSoC pledges to be the one-stop partner guiding startups through real-world complexities. Together, we will build a self-reliant India by leading the semiconductor revolution, not just participating in it.” said Bharath Desareddy, CEO of SmartSoC.

SmartSoC is one of the first Indian companies to partner with multiple foundries, aiming to provide startups with more options so they can select the best fit for their unique design needs. The Post-Silicon Validation services offered by SmartSoC allow startups to rigorously test silicon prototypes against functional, performance, and electrical benchmarks, ensuring compliance with international standards before mass production. These essential services, often unattainable for smaller players due to high costs, are being made accessible to help level the playing field, boost startup credibility, and support their journey to success.

This initiative complements SmartSoC’s ongoing contributions to the DLI Scheme, where the company serves as an engineering collaborator providing end-to-end post-silicon validation, SoC design and verification, physical design, embedded software development, and product engineering support. SmartSoC is actively contributing to advancing India's semiconductor research and development landscape and enabling faster commercialization of indigenous technologies.

“We are proud to partner with SmartSoC Solutions to provide Post-Silicon Validation services and multiple foundry options to startups under the DLI Scheme. This collaboration reinforces our commitment to empowering Indian startups and MSMEs with world-class semiconductor design infrastructure, accelerating innovation, and strengthening India’s self-reliant semiconductor ecosystem,” said Shri. E Magesh, Director General, CDAC, India.

“Providing multiple foundry options and Post-Silicon Validation through partners like SmartSoC ensures startups are able to confidently transition from design to deployable products. By offering complimentary access to expert labs, test infrastructure, and engineering services, initiatives like this reduce both cost and risk, enabling Indian startups to compete globally,” said Dr. SD Sudarsan, Executive Director, CDAC Bangalore Centre.

Aligned with the Government of India’s Semicon India vision and the larger Atmanirbhar Bharat (Self-Reliant India) mission, this collaboration underscores the importance of industry-government partnerships in building a robust innovation ecosystem.

About SmartSoC:

SmartSoC Solutions is a global provider of semiconductor design and embedded engineering services, specializing in turnkey project execution, custom ASIC development, and foundry services. With deep domain expertise and a solutions-driven approach, SmartSoC enables clients to accelerate growth and scale efficiently. Our collaborative, end-to-end approach enables leading semiconductor and system companies to streamline development cycles and bring differentiated silicon solutions to market with precision.

About ChipIN:

ChipIN is an initiative implemented by the Centre for Development of Advanced Computing (C-DAC) under the Design Linked Incentive (DLI) and Chip to Startup (C2S) programes of MeitY, Government of India, aimed at strengthening India’s semiconductor design ecosystem. The ChipIN Centre at CDAC Bangalore is one of the world’s largest and most advanced semiconductor design infrastructure facilities, providing state-of-the-art EDA tools, IPs, prototyping facilities, and high-performance computing (HPC) resources to Indian startups, MSMEs, and academic institutions. This initiative empowers innovators to design and develop complex semiconductor devices in a cost-effective manner. By fostering strong collaboration between industry, academia, and government, ChipIN serves as a national design infrastructure backbone, accelerating innovation, reducing design cycles, and driving indigenous semiconductor development—thereby laying the foundation for a self-reliant and globally competitive semiconductor ecosystem in India.

L&T Semiconductor and C-DAC Collab to Create Make-In-India Integrated Circuits, SoCs and ESDM Solutions for Global Market

L&T Semiconductor Technologies (LTSCT) recently signed a Memorandum of Understanding (MoU) with the Centre for Development of Advanced Computing (C-DAC).

This strategic collaboration aims to drive indigenization efforts and accelerate innovation in areas of mutual interest. Specifically, they will focus on creating Make-in-India Integrated Circuit (IC) / System-on-Chip (SoC) and Electronics System Design & Manufacturing (ESDM) solutions for automotive, industrial, and energy applications.

By reducing reliance on electronic imports, this partnership contributes to strengthening India's economic foundation. Kudos to both organizations for fostering innovation and positioning India as a leader in the semiconductor sector.

By focusing on Make-in-India ICs and SoCs, the collaboration aims to reduce dependency on imports, fostering a more self-reliant semiconductor ecosystem.

Moreover, the focus on automotive, industrial, and energy applications means that critical sectors will benefit from advanced, locally-produced semiconductor solutions, enhancing their efficiency and competitiveness.

The partnership will likely spur innovation and research in advanced semiconductor technologies, positioning India as a hub for cutting-edge developments in this field.

Enhanced local manufacturing and design capabilities can lead to job creation and economic growth, contributing to India’s GDP.

Congratulating both the organisations, Dr Sunita Verma, Group Coordinator, (R&D E&IT) from the Ministry of Electronics and Information Technology (MeiTY), said: “The signing of this MoU between L&T Semiconductor Technologies and C-DAC indicates the Government’s commitment to fostering public-private partnerships that drive innovation and economic growth. This collaboration not only underscores the importance of indigenisation in the semiconductor sector but also paves the way for India to take a leadership role on the global stage. We look forward to the transformative impact that this partnership will have on the nation’s technological landscape.”

Mr Magesh E, Director General – C-DAC, highlighted that the collaboration will significantly boost the semiconductor industry and strengthen the Digital India RISC-V (DIR-V) ecosystem. “The partnership in developing Vega based indigenous ICs and SoCs is set to accelerate the vision of Atmanirbhar Bharat by enabling the development of cutting-edge products and solutions for automotive, industrial, ICT infrastructure and the energy sectors. With a shared vision and the capability to deliver world-class solutions, this collaboration is expected to break new ground in semiconductor and related domains,” he said.

Mr Sandeep Kumar, Chief Executive – LTSCT, said: “This collaboration, led by LTSCT, will create a powerful commercialisation programme for advanced technologies created by C-DAC in semiconductor design & development, embedded software, open-source OS, HPC and power systems. C-DAC’s deep pipeline of indigenous IPs, including the VEGA processor, application design and FPGA validation will be turned into global product opportunities by LTSCT. The joint efforts are anticipated to yield innovative products and solutions that will benefit diverse sectors of the Indian economy while significantly enhancing the nation’s technological capabilities and positioning India as a leader in each of the sectors.”

C-DAC Partners Hyderabad-based SemiCon Firm MosChip and Japan's Socionext for AUM Processor Development

C-DAC (Centre for Development of Advanced Computing) has joined forces with Hyderabad-based semiconductor company MosChip Technologies and Japan-based Socionext Inc. to design and develop a High-Performance Computing (HPC) Processor System on Chip (SoC) called "AUM."

This indigenous processor is based on the Arm architecture and will be built using TSMC's 5nm technology. The AUM processor aims to enhance India's supercomputing capabilities and contribute to solving grand challenge problems of national and global significance.

The AUM Processor will be a groundbreaking achievement in India's pursuit of technological self-sufficiency. Developed by the C-DAC. This indigenous chip is poised to revolutionize supercomputing in India.

The AUM processor is based on the Arm Neoverse V1 design, specifically the v8.4 "Zeus" variant. It features 96 cores and follows a chiplet design. The onboard memory capacity is 64 GB. The AUM processor targets large-scale workloads, including scientific simulations, data analytics, and machine learning applications.

Developed under the National Supercomputing Mission, the AUM processor aims to achieve HPC independence for India—from the processor level up to complete systems and software. It ensures that India's supply chain for HPC parts and systems remains immune from potential imports. The Indian government emphasizes security, ensuring there are no hardware or software backdoors in the AUM processor. Given India's geopolitical context, this focus on security is crucial.

About MosChip Technologies, the semiconductor company has been involved in several notable projects, showcasing their expertise in semiconductor design and system solutions.

It was in early of last month when MosChip Technologies has secured this substantial contract of AUM Processor worth Rs 509.37 crore from the C-DAC. The project involves developing an HPC SoC using cutting-edge 5nm technology. This landmark project not only strengthens MosChip's global positioning but also opens new avenues in both domestic and international markets for Turnkey ASIC solutions.

MosChip collaborate with leading foundries like TSMC, UMC, Global Foundries, and Tower Jazz.

On the other hand, Socionext Inc. is a Japan-based system-on-chip (SoC) company formed in March 2015 from the former system LSI businesses of Fujitsu and Panasonic. They specialize in imaging, networking, and other dynamic technologies that drive today's leading-edge applications. Socionext provides quality semiconductor products based on extensive and differentiated IPs, proven design methodologies, and state-of-the-art implementation expertise, with full support. They contribute to the realization of a sustainable and prosperous society through cutting-edge SoC technology.

Shri E Magesh, Director General, C-DAC, said "The collaboration between C-DAC and MosChip & Socionext to develop cutting-edge HPC processor, which is designed to meet the evolving demands of High-Performance-Computing and related applications, exemplifies the growing synergy between R&D and Industry. This joint effort marks a significant milestone in technological advancement, leveraging C-DAC’s expertise in Supercomputing technology and MosChip’s and Socionext’s capabilities in semiconductor design and manufacturing. The collaboration aims to design, develop and produce indigenous HPC processor that not only meets global standards but also propels India to the forefront in supercomputing arena. This collaboration is also a significant step forward in our efforts to bolster India’s position in the global semiconductor landscape.”

C-DAC is working towards complete indigenization of supercomputing technology. Towards this, C-DAC has developed indigenous compute node RUDRA, Trinetra-Interconnect and System Software stack. Further for complete indigenization of HPC system development, C-DAC is designing an indigenous HPC Processor AUM. Keenheads Technologies, an Indian Startup, has been engaged by C-DAC as Program Management Consultant (PMC) for the project.

Ministry, C-DAC Launches Open Challenge To Create Made-in-India Web Browser with Crypto Token for Digital Sign.

[UPDATED : 18 August 2023]

On Wednesday, Ministry of Electronics & Information Technology (MeitY) had launched the Indian Web Browser Development Challenge (IWBDC), which will be spearheaded by MeitY, Controller of Certifying Authorities (CCA) and C-DAC Bangalore.

The Indian Web Browser Development Challenge is an Open Challenge Competition that is open to all technology enthusiasts, innovators, and developers from all corners of the country to create an Indigenous "Made in India" web browser with its own trust store with an inbuilt CCA India root certificate, cutting edge functionalities and enhanced security & data privacy protection features.

Differing from other browsers available to use, the proposed home-made web-browser would also focus on accessibility and user friendliness, ensuring built-in support for individuals with diverse abilities. Moreover, the browser envisions the ability to digitally sign documents using a crypto token, bolstering secure transactions and digital interactions.

Speaking during the launch event, Sunita Verma, Scientist G & GC (R&D in Electronics & IT) conveyed the message of Shri Alkesh Kumar Sharma, Secretary, MeitY that this challenge marks a significant stride towards an Aatmanirbhar Bharat, designed to strengthen India’s digital sovereignty through the development of the Indian Web Browser.

According to Arvind Kumar, CCA, the crucial role played by CCA in ensuring the trustworthiness and security of digital certificates issued in India and help create a robust PKI infrastructure, enabling secure electronic transactions across the country. However, for SSL certificates, the country has been dependent for SSL certifies issued by Roots of Foreign entities.

Initialising to develop its Own Browser with inbuilt India Root Certificate (by CCA) would help overcoming this challenge. India has moved a step ahead for making the country Internet Resilient which refers to a country’s ability to withstand and recover from various disruptions and threats that may impact its internet infrastructure and connectivity.

Anybody can take part in this challenge and submit idea. There will be three rounds in the whole challenge, after first round i.e. in ideation round 18 entries would be selected.

In the second round 8 participants would be shortlisted to enter into final round. Finally one winner, first runner up and second runner-up would be selected. Throughout the challenge technical mentorship would be provided.

Out of the total prize pool of Rs. 3.41 crore, winner would be facilitate with Rs. One crore. The winner would also be supported further to take the developed browser to next levels.

In order to enter the challenge, please check eligibility criteria and then register here. 

The open challenge launch programme was participated by more than 200 participants from government departments, industry, start-up and academia through on-line and off-line mode. A panel discussion was also organized wherein the queries of the participants were answered by MeitY, CCA and C-DAC officials.

CDAC Partners SoftBank-owned Arm To Support Indian Semiconductor Startups at Every Stage of Prototyping Development

Centre for Development of Advanced Computing (CDAC) on Saturday announced a collaboration with Arm, a SoftBank-owned leading semiconductor IP Company, to broaden the support under the Design Linked Incentive Scheme (DLI) and boost the growth of the semiconductor market in India.

UK based Arm is a chip design company, which was acquired by Japanese conglomerate SoftBank, in September 2016, in a deal worth £23.4bn. At time of acquisition Arm was listed in London and New York. Arm designs the tech behind processors - commonly known as chips - that power devices from smartphones to game consoles. 

As part of Arm's partnership with CDAC, the Arm® Flexible Access for Startups program, which gives $0 license fee access to a broad portfolio of verified Arm IP, tools and training, is now broadening its qualification criteria to welcome applications from startups that qualify under MEITY’s SemiconIndia futureDESIGN DLI scheme.

Arm Flexible Access for Startups allows early-stage startups to move fast, experiment with ease and design with confidence. The program gives startups access to a broad portfolio of extensively verified IP, tools and training, with a $0 license fee to develop system-on-chip (SoC) prototype. This is backed by industry-leading technical support, an extensive ecosystem and a broad developer base for the best chance of success of participating startups in chosen market.

This program for startups provides low-risk, easy access to industry-proven technology, technical support, an extensive ecosystem, and Arm’s broad developer base so silicon startups can move fast, experiment with ease, and design with confidence.

With Arm Flexible Access, startups building products across all markets have the best chance of success with a fast, low-risk journey to building a working prototype, securing the next round of funding, and instilling confidence in potential investors. Arm Flexible Access for Startups also offers technical support and training to rapidly upskill teams, alongside a choice of experienced Arm Approved Design Partners to bring extra capacity and capability along their journey.

Guru Ganesan, President, Arm India, said, "Innovative silicon startups will drive the future of the semiconductor industry as they develop life-changing new technologies in areas from AI to autonomous vehicles and IoT. We are committed to supporting startups, and through the Arm Flexible Access program, we offer the freedom to experiment, innovate and design, so they can become the technology leaders of tomorrow."

E. Magesh, Director General, CDAC, said, "India has a large and growing pool of designers in semiconductor domain and such offerings from semiconductor ecosystem players like Arm will provide a low cost, low risk opportunity to create innovative designs by young entrepreneurs for import substitution and value addition in the electronics sector."

Under this collaboration, CDAC and Arm intend to work towards the following broad objectives:

• Startups selected under DLI will qualify for the Arm Flexible Access for Startups program.
• Arm will provide the startups with access to processor and system IPs, reference designs, GPU, ISP, and AI accelerator IPs, and software development tools.
• Arm will provide access to thousands of Artisan physical IP products supporting multiple foundries and process nodes for physical design and implementation.

The DLI scheme aims to offer financial incentives as well as design infrastructure support across various stages of development and deployment of semiconductor design(s) for Integrated Circuits (ICs), Chipsets, System on Chips (SoCs), Systems & IP Cores and semiconductor linked design(s) over a period of five years.

The DLI Scheme is implemented by C-DAC. Under the DLI Scheme, ChipIN centre has been setup at C-DAC as one stop centre to provide chip design & fabrication services to supported companies.

Five startups/ MSMEs were earlier approved by MeitY for support under the DLI scheme and announced during the 2nd and 3rd DLI Roadshows held earlier this year in Bangalore (February) and Delhi (May). With this announcement, total 7 start-ups under the DLI Scheme will be working on making chip and IP cores for automotive, mobility and computing sectors.

"PARAM ANANTA", the 15th Made in India Supercomputer Under NSM Commissioned At IIT Gandhinagar

PARAM ANANTA, a state-of the art Made-in-India Supercomputer of 838 TeraFlops capacity has been dedicated to the nation today, under National Supercomputing Mission (NSM) — a joint initiative of Ministry of Electronics and Information Technology (MeitY) and Department of Science and Technology (DST).

"Ananta", the name of the supercomputer, literally means ‘endless’ or ‘limitless’. The logo design symbolises the Sudarshan Chakra in the form of the Sun along with data grid mountains merging in perspective with the limitless horizon.

The new facility will provide a tremendous amount of computational power to the scientific community of IITGN as well as the academic institutions and industries in the vicinity of the Institute to take their Research and Development (R&D) efforts to a global scale: IITGN pic.twitter.com/NBykv7T7h2

— DeshGujarat (@DeshGujarat) May 30, 2022

The supercomputer, which is 15th supercomputer under NSM till date, was commissioned at Indian Institute of Technology - Gandhinagar (IIT Gandhinagar) by Sunita Verma, Group Coordinator & Scientist 'G', Ministry of Electronics and Information Technology (MeitY) and Prof. Amit Prashant, officiating Director, IIT Gandhinagar.

A portion of the total compute power shall also be shared with the nearby academic and research institutes as per the mandate of NSM. Further, NSM has sponsored a number of application research projects using this Supercomputing facility involving researchers for and other Indian institutes and industries. Overall, this Supercomputing facility will provide a major boost to the research and development initiatives in Indian academia and industries to reach a position of global esteem.

Under NSM, till date 15 supercomputers have been installed across the nation with aggregate compute capacity of 24 petaflops. All these supercomputers are completely Made in India.

PARAM ANANTA supercomputing facility is established under Phase-2 of the NSM, where in majority of the components used to build this system have been manufactured and assembled within the country, along with an indigenous software stack developed by C-DAC, in line with the Make in India initiative.

Prior to this, a Petascale Supercomputer "PARAM Shakti" at IIT Kharagpur, was unveiled in March this year. Earlier in year 2020, the government has announced a 100 Artificial Intelligence (AI) PetaFlops supercomputing system, PARAM Siddhi – AI, created and installed in C-DAC facility by NVIDIA.

PARAM ANANTA is equipped with a mix of CPU nodes, GPU nodes, High Memory nodes, High throughput storage and high performance Infiniband interconnect to cater the computing needs of various scientific and engineering applications.

The system is based on Direct Contact Liquid Cooling technology to obtain a high power usage effectiveness and thereby reducing the operational cost.  Multiple applications from various scientific domains such as Weather and Climate, Bioinformatics, Computational Chemistry, Molecular Dynamics, Material Sciences, Computational Fluid Dynamics etc. have been installed on the system for the benefit of researchers. This high end computing system will be a great value addition for the research community.

PARAM ANANTA Supercomputing Facility will be of great benefit to IIT Gandhinagar to pursue the Research and Development (R&D) activities in multidisciplinary domains of science and technology at the Institute, including, but not limited to, Artificial Intelligence (AI), Machine Learning (ML), and Data Science; Computational Fluid Dynamics (CFD); Bio-engineering for Genome Sequencing and DNA studies; Computational Biology and Bioinformatics used in prediction and detection of gene networks; Atomic & Molecular Sciences that helps in understanding how a drug binds to a particular protein.

Besides, the supercomputing facility will also be beneficial for studies & research in Climate Change and Environment studies for extreme weather predictions and simulation of models which can predict the onset of a cyclone;  Energy studies which will help in carrying out design simulation and optimization of energy conversion devices at various scales; Fire Dynamics Simulation; Nanotechnology; Robotics; Applied mathematics; Astronomy and Astrophysics; Material Sciences; Quantum Mechanics; Studies on Civil Engineering and structural mechanics to understand the dynamic behaviour of buildings, bridges; and complex structure.

India Democratize Semiconductor Chip Designing, Enables Chip Centre At C-DAC To Be Accessed Remotely

Now Anyone from Anywhere can Design Chips & innovate as MeitY brings Design Infrastructure to Doorstep

India is in process of democratizing semiconductor chip designing by bringing design infrastructure to doorstep so that anyone from anywhere can design chips and can innovate. Ministry of Electronics and Information Technology (MeitY) has just announced that India Chip Centre at CDAC would pool the Design licenses centrally to be made available to students at remote locations for designing chips.

Last month, MeiTY announced the formation of an advisory committee for Semiconductor Ecosystem, comprising industry experts, that include Vinod Dham, who is known as father of Pentium Chip and HCL Co-founder - Dr. Ajai Chowdhry.

In a latest now, MeitY, with its series of graded and proactive steps, is in the process of systematic overhaul of semiconductor design approach at 120 premier academic institutions across the country to debut an era of creative enablement where anyone with innate skills, anywhere in the country can get the semiconductor chips designed.

Earlier in 2021, a pilot deployment was successfully tested by MeitY under Special Manpower Development Programme for Chips to System Design (SMDP-C2SD), wherein a centralized design facility at C-DAC was enabled for remote access by over 50,000 engineering students at 60 academic institutions for designing chips. 

Leapfrogging, MeitY now intends to make accessible a centralized chip design infrastructure to be made available at India Chip Centre setup at C-DAC, to train 85000+ B.Tech, M.Tech and PhD students at 120 academic institutions across the country in chip design area for next 5 years.

For making available the chip design infrastructure at India Chip Centre (C-DAC), leading industry vendors from EDA (Electronic Design Automation), Electronic Computer-Aided Design (ECAD), IP Core and Design solutions Industry are being partnered with. Specific collaborative arrangements are being made available with Synopsys, Cadence Design Systems, Siemens EDA, Silvaco & other leading tool vendors, IP & design solution providers and Fab aggregators.

At centralized design facility hosted at India Chip Centre (C-DAC), not only the most advanced tools for entire chip design cycle (i.e. Front-end design, Back-end design, PCB design & analysis etc. for Digital, Analog, RF & Mixed Signal designs), going up to 7nm or advanced node but also an arrangement of instructor-led/ online trainings on design flows by industry professionals are being made available for next 5 years.

This centralized facility at India Chip Centre (C-DAC), one of the biggest of existing facilities, offering plethora of design flows, aims to bring the chip design infrastructure at door-steps of over 85,000 students at 120 academic institutions. Taking advantage, several academic start-ups will mushroom across the country, cross the initial entry barriers and pave the way for entrepreneurship/ startup-led design & innovations ecosystem in the country making indigenous IP Cores, Chips, System on Chip (SoCs), Systems for different application areas like 5G/ IoT, AI/ ML, Automotive & Mobility sector etc. in India, for the World.

As SemiconIndia 2022 concluded successfully last week, most of the global semiconductor leaders (like Intel, Micron, Qualcomm, LAM Research etc) not only highlighted the contribution of their Indian R&D centres, which are now the biggest centres out of their headquarter locations but also acknowledged the semiconductor design strength in our country, which now makes up for 20% of the world’s engineers.

Shri Ashwini Vaishnaw, Minister for Electronics & Information Technology envisions making available a design talent pool of highly skilled engineers for turning India into a semiconductor hub through the Chips to Startup (C2S) Programme and other initiatives in Semiconductor policy. This will strengthen & supplement the Indian talent pool designing the leading-edge chips for semiconductor giants with complete ownership of some of these chips in the country. Speaking at SemiconIndia 2022, he highlighted that India's democracy and talent pool sets it apart from other countries fighting for chip sovereignty.

Many co-development pacts were announced at SemiconIndia 2022 last week by Shri Rajeev Chandrasekhar, Minister of State for Electronics & Information Technology including Digital India RISC-V (DIR-V) Program, aiming to catalyze India’s semiconductor ecosystem. These announcements, coupled with the fact that India has just scored a century of Unicorns this week and the steps taken to democratize the chip design across the country, shall trigger the next wave of Startups and unicorns from semiconductor design space in the country.

Petascale Supercomputer PARAM Shakti at IIT Kharagpur Dedicated to the Nation

"PARAM Shakti", a Petascale Supercomputer " at IIT Kharagpur, has been dedicated to the nation under Indian government's National Supercomputing Mission (NSM) - a joint initiative of Ministry of Electronics and Information Technology (MeitY) and Department of Science and Technology (DST). Under NSM, India aims to expand and develop the supercomputing capacity by manufacturing its own supercomputers in the country.

Petascale computing refers to computing systems capable of calculating at least 10¹⁵ floating point operations per second (1 petaFLOPS). Petascale computing allowed faster processing of traditional supercomputer applications. The first system to reach this milestone was the IBM Roadrunner in 2008.

The PARAM Shakti facility is an outcome of MoU signed between IIT Kharagpur and CDAC in March 2019, according to which this state-of the art Supercomputing Facility with 17680 CPU cores along with 44 GPUs has been established now.

The supercomputer was inaugurated yesterday (March 27, 2022) by the Governor, of West Bengal in the gracious presence of Prof V K Tewari, Director, IIT Kharagpur; Dr. Sivaji Chadaram, Director, DST and Col A.K Nath (Retd), Director General and Executive Director, CDAC.

PARAM Shakti supercomputing facility would accelerate the research and development activities in multidisciplinary domains of computational and data sciences as it provides large-scale computing power to the user community of IIT Kharagpur and neighbouring academic and R&D institutes.

This facility has pioneered in using RDHX based efficient cooling system to obtain a high power usage effectiveness. This system has been tested extensively by both IIT Kharagpur and CDAC for commercial, open-source and in-house software pertaining to diversified applications.

In early this month, an another indigenous Petascale Supercomputer “PARAM Ganga” was established at IIT Roorkee.

Earlier in 2020, the government has announced a 100 Artificial Intelligence (AI) PetaFlops supercomputing system, PARAM Siddhi – AI, created and installed in C-DAC facility by NVIDIA. 

In October 2020, it was reported that India's total network of Superconputing performance is yet to reach 16 Petaflops (PF), is less than of Piz Daint, a Switzerland -based supercomputer , which has performance power of 27.1 Petaflops (PF) [theoretical peak performance] and ranked 21st in TOP500 ranking of supercomputers until last November.

IIT Kharagpur has also established the Centre for Computational and Data Science with a mandate to train the researchers in Supercomputer accelerated R&D. The new high-performance computational facility would aid researchers to solve large-scale problems of different fields of Science and Engineering.

Some of the identified focus areas in which this supercomputing based research will be of great value addition are: Computational Fluid Dynamics, Artificial Intelligence, Big Data Analytics, Climate Change & Digital Earth, Computational Biology, Cryptography & Security, Smart Infrastructure & Sustainable Cities, Smart Materials etc.

Furthermore, NSM has sponsored a number of application research projects using this Supercomputing facility involving researchers for IIT Kharagpur and other Indian institutes and industries.

SIDBI Signs MoU with CDAC to Strengthen Cyber Security Capabilities

Small Industries Development Bank of India (SIDBI), the principal financial institution engaged in the promotion, financing and development of Micro, Small & Medium Enterprises (MSMEs), today signed a Memorandum of Understanding (MOU) with the Centre for Development of Advanced Computing (C-DAC), a premier R&D organization under the Ministry of Electronics and IT, Government of India, in a virtual event.

SIDBI and C-DAC will collaborate to explore innovation and use of emerging technologies in the areas of Cyber Security, AI/ML, block chain, etc. and related training and capacity building aspects in the Banking Sector.

The MoU was signed by Shri Sudatta Mandal, Deputy Managing Director, SIDBI, and Shri Magesh E, Executive Director, C-DAC, in the presence of Shri Satheesh G, Senior Director and Head, Cyber Security Group, Shri Senthilkumar K.B and Dr. Dittin Andrews, Joint Directors from C-DAC and Shri Ravi Tyagi, Chief General Manager, SIDBI, Shri Paramendra Tiwary, Chief Technology Officer, SIDBI, Shri Sudhir Tandon, General Manager, SIDBI.

Since its formation in 1990, SIDBI has been impacting the lives of citizens across various strata of the society through its integrated, innovative and inclusive approach. Be it traditional, domestic small entrepreneurs, bottom-of-the-pyramid entrepreneurs, to high-end knowledge-based entrepreneurs, SIDBI has directly or indirectly touched the lives of Micro and Small Enterprises (MSEs) through various credit and developmental engagements. SIDBI 2.0 carries the vision of inclusive, innovative and impact-oriented engagements.

To know more, check out: https://www.sidbi.in

Application Invited from Startups and MSMEs under Chips to Startup (C2S) Programme of MeitY

MeitY invites applications under the Chips to Startup (C2S) Programme from academia, R&D organisations, startups and MSMEs

In line with Prime Minister Shri Narendra Modi’s plan to transform India into the next semiconductor hub, the Ministry of Electronics and Information (MeitY) has sought applications from 100 academia, R&D organisations, start-ups and MSMEs under its Chips to Startup (C2S) Programme.

The Chips to Startup (C2S) Programme aims to train 85,000 number of high-quality and qualified engineers in the area of Very large-scale integration (VLSI) and Embedded System Design as well as result in development of 175 ASICs (Application Specific Integrated Circuits), Working Prototypes of 20 System on Chips (SoC) and IP Core repository over a period of 5 years. This will be a step towards leapfrogging in the Electronics System Design & Manufacturing (ESDM) space by way of inculcating the culture of SoC/ System Level Design at Bachelors, Masters and Research level and act as a catalyst for growth of Start-ups involved in fabless design.

The programme would be implemented at about 100 academic institutions/R&D organisations across the Country (including IITs, NITs, IIITs, Government/Private Colleges and R&D Organisations). Startups and MSMEs can also participate in the programme by submitting their proposals under Academia- Industry Collaborative Project, Grand Challenge/ /Hackathons/RFP for development of System/SoC/IP Core(s).

The C2S Programme addresses each entity of the value chain in electronics viz. quality manpower training, research and development, hardware IPs design, System design, application-oriented R&D, Prototype design and deployment with the help of academia, industry, start-ups and R&D establishments.

Under the Programme, based on the Institutions’ expertise, Technology Readiness Level (TRL) and design experience acquired during earlier SMDP Programmes, proposals are invited in three different categories, i.e., Design and Development of Systems/SoCs/ASICs/Reusable IP Core(s), Development of Application Oriented Working Prototype of IPs/ASICs/SoCs, and Proof of Concept oriented Research and Development of ASICs/FPGAs.

C-DAC (Centre for Development of Advanced Computing), a scientific society operating under MeitY, will serve as the nodal agency for the programme.

Online applications are open at the Chips to Startup (C2S) website until January 31, 2022.

The project proposals should be submitted at C2S portal (www.c2s.gov.in) in the format prescribed at the portal. The institutions applying under the programme should meet the eligibility criteria defined at the portal and should be in line with the proposals’ guidelines.

India’s Fastest HPC-AI Supercomputer PARAM Siddhi – AI to be Commissioned by C-DAC and NVIDIA

C-DAC to Commission India’s Fastest HPC-AI Supercomputer ‘PARAM Siddhi – AI’, Built with NVIDIA DGX A100 Systems Connected with NVIDIA Mellanox HDR InfiniBand Network, C-DAC HPC-AI Engine, AI Software Stack and Cloud Platform.

Representative

NVIDIA today announced that the Centre for Development of Advanced Computing (C-DAC) will be commissioning India’s largest HPC-AI supercomputer ‘PARAM Siddhi – AI’ -- a machine with 210 AI Petaflops (6.5 Petaflops Peak DP), based on the NVIDIA DGX SuperPOD reference architecture comprising of 42 NVIDIA DGX A100 systems, connected with NVIDIA Mellanox HDR InfiniBand networking along with indigenously developed HPC-AI engine, Software Frameworks, Cloud Platform by C-DAC.

With the approval of Shri Ravi Shankar Prasad, Hon’ble Minister of E&IT and L&J, Shri Ajay Prakash Sawhney (Secretary, MeitY), Prof Ashutosh Sharma (Secretary, DST) and recommendation of National Supercomputing Mission (NSM – a Government of India Initiative) Technical Advisory Committee (TAC) chaired by Dr V K Saraswat, Member, Niti Aayog this initiative will put India’s leadership on top of global AI supercomputing research and innovation, thanks to the dynamic efforts of Shri Abhishek Das, young innovative Scientist and Program Director (HPC-AI Infrastructure Development) at C-DAC for conceiving the idea, designing the architecture of the largest HPC-AI Infrastructure in India.

Dr Hemant Darbari, Director General, C-DAC said, “PARAM Siddhi – AI, the State-of-the-Art large-scale HPC-AI scalable infrastructure that will be established under National Supercomputing Mission (NSM) at Centre for Development of Advanced Computing (C-DAC) with support from Niti Aayog, Ministry of Electronics and IT, Department of Science and Technology, Government of India using NVIDIA Next Generation technology, C-DAC software stack and Cloud platform will play a pivotal role in developing a vibrant ecosystem for research and innovation in science and engineering. With three decades of expertise in AI and augmenting the AI and Language Computing Mission Mode Program of C-DAC, this infrastructure will accelerate experiments and outcomes for India specific grand challenge problems in Health Care, Education, Energy, Cyber Security, Space, Automotive and Agriculture. It will catalyze partnerships with the Academia, Industry, MSMEs and Start-ups.”


“NVIDIA is committed to supporting nations across the globe in their mission to advance the frontiers of AI-enabled research,” said Charlie Boyle, General Manager and Vice-President of DGX systems at NVIDIA. “The turnkey NVIDIA DGX SuperPOD architecture is central to helping C-DAC deploy its supercomputer in record time. With this new AI supercomputer, C-DAC will be able to unleash AI innovation at incredible scale to help India address some of its most important challenges now, and in the future.”

IETE Inaugurates Centre of Excellence for Cyber Security

The Institution of Electronics and Telecommunication Engineers (IETE) inaugurated Centre of Excellence for Cyber Security. During the occasion, Lt. Gen. (Retd.) Dr. Rajesh Pant, National Cyber Security Coordinator (NCSC), PMO, Government of India, was the chief guest at the inaugural function.

While speaking at the inauguration of the 'Centre of Excellence: Cyber Security and Critical Infrastructure Security', Lt. Gen. (Retd.) Dr. Rajesh Pant said, "Cyber Security has become very important during COVID-19. We are passing through a very serious situation at the moment. This timely step by 'The Institution of Electronics and Telecommunication Engineers' (IETE) India will have full support from my Department."

Lt. Gen. (Retd.) Dr. Rajesh Pant in his address advised IETE to focus around Hardware Security and align its efforts with Mission of Government of India like 'National Quantum Mission'.

Setting up of the 'Centre of Excellence: Cyber Security and Critical Infrastructure Security', is part of the initiative of IETE's future growth strategy.

While conveying his sincere gratitude to the Chief Guest Lt. Gen. (Retd.) Dr. Pant for his valuable advice on bringing a focus to specific area of Cyber Security, particularly hardware security, Dr. J.W. Bakal, president, IETE shared a broad outline of the CoE. "IETE's focus is to support Government of India's effort in creating a strong ecosystem for Cyber Security in the areas of IoT, Smart City, Industry 4.0 and Hardware Security," said Dr. Bakal. He also emphasized that the connected ecosystem covers smart factories, smart grid and smart supply chain therefore issues of data security and privacy are of great importance.

Dr. N. Sarat Chandra Babu, Executive Director, Society for Electronic Transactions and Security (SETS) Chennai, in this keynote address gave an overview of current and emerging trends in Cyber Security. In addition to industry-academia association; industry led applied research, he emphasized on collaboration amongst R&D organizations to arrive at a holistic indigenous solution in cyberspace. "We have to address the growing challenges of cyber threats by training a large pool of skilled manpower. For this, an appropriate training infrastructure as to be in place. CoE by IETE is a step in this direction," said Dr. Sarat Babu. According to him there is a need for preparedness of the nation in terms of Cyber Security in Quantum Era by focusing on Post Quantum Cryptography and Quantum Key Distribution Technologies.

On this occasion, a tech-webinar was also organized on Cyber Attacks & Mitigation Strategy and Vulnerability & Penetration Testing. Dr. T.R. Reshmi and S. Karthikeyan, Scientists, SETS Chennai delivered a holistic perspective on the above important topics. This session was followed by an interactive Q&A session.

Dr. Shiv Kumar, Co-Chair, Skill Development and Industrial Committee, IETE thanked IETE Governing Council for the support and guidance on CoE. He also thanked Electronic Sector Skill Council (ESSCI), Telecom Sector Skill Sector Council (TSSC), Information Security Education and Awareness (ISEA), Centre for Development of Advanced Computing (C-DAC) for extending their active support and he also thanked the participants.

During their address, Dr. Bakal and Dr. Sarat Babu applauded the initiative taken by Dr. Kumar for the efforts in launching the CoE.

About IETE

Founded in 1953, the Institution of Electronics and Telecommunication Engineers (IETE) is a leading professional society devoted to the advancement of Science & Technology in Electronics, Telecommunications, Information Technology, Computer Science and other related disciplines. IETE 65 Centres spread all over India including one at Perth (Australia) and Kathmandu (Nepal) respectively.

To keep pace with technological development and achieve the mission of advancing the profession, it organizes conferences, conventions, symposia, seminars, workshops, publications and brain storming sessions for continued knowledge upgradation of its members.

About SETS

Society for Electronic Transactions and Security (SETS) is an initiative of the Office of the Principal Scientific Advisor (PSA) to the Government of India. An idea to form a specialized organization, in the area of information security was conceived of by Dr. A.P.J. Abdul Kalam and implemented by Dr. R. Chidambaram through the Office of the PSA.

It was set up for the purpose of nucleating, sensitizing and developing provable security designs that can protect the information wealth of the country and that can be used in applications of Information Security products and services.

India to Get 14 New Supercomputers under ₹ 4,500 Cr Supercomputing Mission

The Department of Science and Technology (DST), a department within the Ministry of Science and Technology in India, has issued a official statement, where it said that 14 new supercomputers will be deployed this year under Rs 4,500 crore-National Supercomputing Mission (NSM).

According to the DST statement, by the end of 2020 14 new super-computing systems would be installed at various national-level research laboratories and academic institutions.

The 1st indigenously assembled supercomputer, called Param Shivay, was installed in IIT-BHU and was inaugurated by the Prime Minister last year in February. Similar systems Param Shakti and Param Brahma were installed at IIT-Kharagpur in March last year. This is equipped with applications from domains like Weather and Climate, Computational Fluid Dynamics, Bioinformatics, and Material science.

Three more supercomputers are planned to be installed by April 2020, one each at IIT-Kanpur, JN Centre for Advanced Scientific Research, Bengaluru, and IIT-Hyderabad. This will ramp up the supercomputing facility to 6 PF.

Going forward, 11 new systems are likely to be set up in different IITs, NITs, National Labs, and IISERs across India by December this year, which will have many sub-systems manufactured and microprocessors designed in India which will bring in a cumulative capacity of 10.4 petaflops.

Steered jointly by the Ministry of Electronics and IT (MeitY) and DST and implemented by the Centre for Development of Advanced Computing (C-DAC), Pune and the Indian Institute of Science (IISc), Bengaluru, the NSM mission was targeting to establish a network of supercomputers ranging from a few Tera Flops (TF) to Hundreds of Tera Flops (TF) and three systems with greater than or equal to 3 Peta Flops (PF) in academic and research institutions of National importance across the country by 2022.

This network of Supercomputers envisaging a total of 15-20 PF was approved in 2015 and was later revised to a total of 45 PF (45000 TFs), a jump of 6 times more compute power within the same cost and capable of solving large and complex computational problems.

To recall, in August 2018 India's first industrial Artificial Intelligence (AI) supercomputer was housed at CEERI's New Delhi campus. The system is a joint effort from Central Electronics Engineering Research Institute (CEERI) in Delhi and US-based chip-designer NVIDIA Corp.