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| VIHAAN Chip (Image ~ www.aheesa.com) |
Chennai-based Aheesa Digital Innovations has achieved first-pass silicon success with its indigenous broadband networking chip ‘VIHAAN’, built using India’s VEGA microprocessor. The milestone, backed by the Design Linked Incentive (DLI) Scheme, positions VIHAAN for production tape-out in 2027 and strengthens India’s domestic semiconductor ecosystem.
The Design Linked Incentive (DLI) Scheme is empowering Indian startups to design semiconductors for diverse strategic and commercial uses. Applications span satellite communications, drones, surveillance systems, defence and aerospace platforms, automotive electronics, IoT devices, LED drivers, AI solutions, telecom infrastructure, and smart meters.
Aheesa Digital Innovations, an Indian fabless semiconductor startup, develops chips for broadband networking and security. Its flagship SoC ‘VIHAAN’, purpose‑built for fibre broadband, was taped out on Republic Day and achieved first‑pass silicon success on Independence Day 2026. The chip now advances toward production tape‑out, targeted for 2027.
Key Highlights
- Startup: Aheesa Digital Innovations (Chennai-based, fabless semiconductor firm)
- Chip: VIHAAN – broadband networking System-on-Chip (SoC)
- Processor Core: Built on VEGA microprocessor (RISC-V architecture, developed by C-DAC under MeitY)
- Milestone: Taped out on Republic Day 2026, achieved first-pass silicon success on Independence Day 2026
- Target: Production tape-out scheduled for 2027
- Funding: Raised ₹40 crore earlier in 2026 from TNIFMC via TNESSF and private investors
- Applications: Designed for fiber broadband networks, enabling last-mile connectivity for homes and offices
Technical & Strategic Significance
| Feature | Details |
|---|---|
| Architecture | RISC-V based VEGA processor core |
| Process Node | 28nm broadband networking SoC |
| Functions | Integrates compute, broadband access, and system control |
| Target Use | Optical fiber access networks, telecom operators |
| Strategic Value | Reduces reliance on foreign chip designs; supports Atmanirbhar Bharat goals |
| Ecosystem Impact | Part of >30 chip tape-outs under DLI Scheme; contributes to India’s $100M+ VC-backed semiconductor design growth |
Broader Context
- DLI Scheme Impact: Over 30 chip design tape-outs achieved across foundries; startups raised $100M+ venture capital
- Government Support: Chip-design tools provided to 455 organizations (350 academic institutions + 105 startups)
- C2S Programme: 245 chip designs taped out by 71 academic institutions, building skilled manpower for India’s semiconductor future
Challenges & Trade-offs
- Production Timeline: Commercial rollout only expected post-2027, leaving a gap before market adoption
- Global Competition: Competing against established players (ARM, Intel, Broadcom) with mature ecosystems
- Scaling Risks: Transition from prototype to mass production requires robust fabrication partnerships and supply chain resilience












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